FPGA Implementation of Tunable FFT For SDR Receiver

The purpose of this paper is to compare competing techniques for wideband channelisation, and to assess the flexibility of each of these methods in the context of a software defined radio (SDR) receiver. Distinction is drawn between architectures where all channels are equally spaced and of equal bandwidth, and those architectures which afford greater flexibility. The architecture requires that an input signal be separated into a number of different frequency channels. If these channels are of equal width and equally spaced, then techniques such as the Fast Fourier Transform (FFT) or the pipelined frequency transform (PFT) can be employed. The most common solution is to employ a number of digital down converters (DDC) each responsible for an individual channel. The tunable pipelined frequency transform (TPFT) provides similar functionality to a stack of DDCs. It gives the user freedom to specify channels by centre frequency and bandwidth define filter characteristics and reconfigure to another frequency plan as required. Furthermore, spectral shaping masks can also be directly applied onto the outputs within the architecture itself. This paper describes the TPFT architecture and will highlight the advantages of this technique over competing solutions. The proposed architecture is coded using VHDL and the simulation and synthesis reports are discussed.